1. Field of the Invention
The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and apparatus for generating multiple checkpoints in a processor that supports speculative-execution.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
When a memory reference, such as a load operation, generates a cache miss, the subsequent access to level-two (L2) cache (or memory) can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.
A number of techniques are presently used (or have been proposed) to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster. Moreover, constraints on the number of physical registers that can be used for register renaming purposes during out-of-order execution also limit the effective size of the issue queue.
Some processor designers have proposed using speculative-execution to avoid the pipeline stalls associated with cache misses. Two such proposed speculative-execution modes are: (1) execute-ahead mode and (2) scout mode.
Execute-ahead mode operates as follows. During normal execution, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can be used to return execution of the program to the point of the instruction. Next, the system executes subsequent instructions in the execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order.
If the unresolved data dependency is resolved during execute-ahead mode, the system enters a deferred execution mode, wherein the system executes deferred instructions. If all deferred instructions are executed during this deferred execution mode, the system returns to normal-execution mode to resume normal program execution from the point where the execute-ahead mode left off. Alternatively, if all deferred instructions are not executed, the system returns to execute-ahead mode until the remaining unresolved data dependencies are resolved and the deferred instructions can be executed.
If the system encounters a non-data-dependent stall condition while executing in normal mode or execute-ahead mode, the system moves into scout mode. In scout mode, instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the processor. When the launch point stall condition (the unresolved data dependency or the non-data dependent stall condition that originally caused the system to move out of normal-execution mode) is finally resolved, the system uses the checkpoint to resume execution in normal mode from the launch point instruction (the instruction that originally encountered the launch point stall condition).
By allowing a processor to continue to perform work during stall conditions, speculative-execution can significantly increase the amount of computational work the processor completes.
Unfortunately, the gains in computational work achieved using execute-ahead mode can be lost when the processor encounters a condition which requires the processor to return to a remote checkpoint (a checkpoint which was generated many instructions beforehand). During execute-ahead mode the processor can potentially execute thousands of instructions. Upon returning to the remote checkpoint, the processor discards the results of these speculatively executed instructions and must eventually re-compute the instructions during normal execution mode. When forced to redo this large amount of computational work, the processor loses the main benefit of execute-ahead mode.
Hence, what is needed is a mechanism that prevents the loss of a large amount of computational work when a processor returns to a checkpoint during execute-ahead mode.